For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Non-volatile semiconductor memories typically use stacked floating gate type field-effect-transistors. In such transistors, electrons are injected into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed. An oxide-nitride-oxide (ONO) stack is used as either a charge storing layer, as in a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) transistor, or as an isolation layer between the floating gate and control gate, as in a split gate flash transistor. FIG. 1 illustrates a cross-sectional view of a conventional nonvolatile charge trap memory device.
Referring to FIG. 1, semiconductor device 100 includes a SONOS gate stack 104 including a conventional ONO portion 106 formed over a silicon substrate 102. Semiconductor device 100 further includes source and drain regions 110 on either side of SONOS gate stack 104 to define a channel region 112. SONOS gate stack 104 includes a poly-silicon gate layer 108 formed above and in contact with ONO portion 106. Poly-silicon gate layer 108 is electrically isolated from silicon substrate 102 by ONO portion 106. ONO portion 106 typically includes a tunnel oxide layer 106A, a nitride or oxy-nitride charge-trapping layer 106B, and a top oxide layer 106C overlying nitride or oxy-nitride layer 106B.
One problem with conventional SONOS transistors is the poor quality tunnel oxide layer 106A obtained when attempting to scale such devices. Batch processing equipment is conventionally used to grow tunnel oxide layer 106A. Such a process may be sufficient for relatively thick tunnel oxide layers. However, attempts to grow a thinner tunnel oxide layer 106A, i.e. to scale tunnel oxide layer 106A, in batch processing equipment has resulted in tunnel oxide layers of unacceptably low quality and/or poor thickness uniformity. FIG. 2 illustrates a cross-sectional view of a conventional oxidation chamber of a batch-processing tool.
Referring to FIG. 2, a batch oxidation chamber 200 includes a carrier device 204 to hold a plurality of semiconductor wafers 202. In growing a tunnel oxide layer on each of the plurality of semiconductor wafers 202, both inter- and intra-wafer tunnel oxide growth variations can occur. These variations can result because the relative arrangement of each wafer of the plurality of semiconductor wafers 202 varies with respect to the coordinates of batch oxidation chamber 200. Furthermore, long temperature ramp times and stabilization times used to heat the plurality of semiconductor wafers 202 in batch oxidation chamber 200 can cut into the thermal budget of the plurality of semiconductor wafers 202. Additionally, batch oxidation chamber 200 is usually restricted to processing temperatures of 800 degrees Celsius or lower.